Tft, method for manufacturing the same, and tft array

ABSTRACT

A TFT, a method for manufacturing the same, and a TFT array are provided. The method for manufacturing a TFT includes the following. A gate insulation layer is formed on a gate electrode layer. A MOS layer and an etching protective layer are sequentially deposited on the gate insulation layer. A metal electrode layer is formed on the gate insulation layer and the etching protective layer. The metal electrode layer is etched to obtain a source electrode layer and a drain electrode layer. The etching protective layer is etched to expose the MOS layer.

RELATED APPLICATION

The present application is a national phase of International ApplicationNo. PCT/CN2019/119807, filed Nov. 21, 2019.

TECHNICAL FIELD

This disclosure relates to the field of semiconductor optoelectronictechnology, and more particularly to a thin-film transistor (TFT), amethod for manufacturing a TFT, and a TFT array.

BACKGROUND

With development of display technology, various display devices such asliquid crystal display (LCD) devices, organic electroluminescencedisplay (OLED) devices, or inorganic electroluminescence display (suchas mini-LED, or micro-LED) devices are widely used. Each liquid crystalpixel in the LCD device is driven by a thin-film transistor (TFT)integrated behind the pixel, which is possible to display information ata high speed, a high brightness, and a high contrast and is currentlyone of the most excellent color display devices.

The TFT includes a semiconductor layer. The semiconductor layer hassource/drain regions doped with high-concentration dopants, a channelregion formed between the source/drain region, a gate disposedcorresponding to the channel region and insulated from the semiconductorlayer, and a source/drain in contact with each source/drain region. Inan existing TFT, a metal oxide semiconductor (MOS) material is oftenused for a gate electrode channel. The MOS material includes In—Gaoxide, In—Zn oxide, or In-M-Zn oxide (where M can be Al, Ga, Y, La, Ce,Sn, or the like). An amorphous MOS composed of indium, gallium, zinc,and oxygen (that is, In—Ga—Zn—O, and “IGZO” for short) is usually used,and on the MOS of IGZO, source-drain electrodes are formed. When thesource-drain electrodes are etched, an etchant will damage the MOS ofIGZO, and as a result, the performance of the entire TFT will beadversely affected.

Therefore, the manner in the related art is in a need of improvement.

SUMMARY

Considering disadvantages of the related art, implementations provide aTFT, a method for manufacturing a TFT, and a TFT array, which can solvea problem that a MOS of IGZO will be damaged by an etchant duringetching of source-drain electrodes and thus the performance of theentire TFT will be adversely affected.

In a first aspect, a method for manufacturing a TFT is provided. Themethod includes the following. A gate insulation layer is formed on agate electrode layer. A MOS layer and an etching protective layer aresequentially deposited on the gate insulation layer. A metal electrodelayer is formed on the gate insulation layer and the etching protectivelayer. The metal electrode layer is etched to obtain a source electrodelayer and a drain electrode layer. The etching protective layer isetched to expose the MOS layer.

In some implementations, the metal electrode layer is etched to obtainthe source electrode layer and the drain electrode layer as follows. Aphotoresist material layer is formed on the metal electrode layer, andthe photoresist material layer is patterned to obtain a photoresistlayer. The metal electrode layer is etched, and a pattern of thephotoresist layer is transferred onto the metal electrode layer toobtain the source electrode layer and the drain electrode layer.

In some implementations, the photoresist material layer is formed on themetal electrode layer, and the photoresist material layer is patternedto obtain the photoresist layer as follows. The photoresist materiallayer is formed on the metal electrode layer. The photoresist materiallayer is exposed and developed and a part of the photoresist materiallayer is removed to obtain the photoresist layer, where the part of thephotoresist material layer removed is on a portion of the metalelectrode layer in contact with the etching protective layer.

In some implementations, the method further includes the following afterthe metal electrode layer is etched to obtain the source electrode layerand the drain electrode layer. The photoresist layer on the metalelectrode layer is removed. An indium tin oxide (ITO) layer is formed onthe source electrode layer, the drain electrode layer, and a gateelectrode channel.

In some implementations, the method further includes the following afterthe ITO layer is formed on the source electrode layer, the drainelectrode layer, and the gate electrode channel. A photoresist materiallayer is formed on the ITO layer, and the photoresist material layer ispatterned to obtain a photoresist layer. The ITO layer is etched, and apattern of the photoresist layer is transferred onto the ITO layer.

In some implementations, the method further includes the following afterthe etching protective layer is etched to expose the MOS layer. Aprotective layer is formed on the source electrode layer, the drainelectrode layer, and a gate electrode channel.

In some implementations, the etching protective layer is a titaniummetal layer, and the etching protective layer has a thickness of 150˜250Å.

In some implementations, the metal electrode layer has a double-layeredmetal structure including an aluminum metal layer and a molybdenum metallayer, where the aluminum metal layer has a thickness of 2500˜3000 Å,and the molybdenum metal layer has a thickness of 300˜500 Å.

In a second aspect, a TFT is provided. The TFT includes a gate electrodelayer, a gate insulation layer disposed on the gate electrode layer, aMOS layer disposed on the gate insulation layer, an etching protectivelayer disposed on the MOS layer, and a source electrode layer and adrain electrode layer disposed on the gate insulation layer and spacedapart at two ends of the etching protective layer.

In some implementations, the etching protective layer is disposed on asurface of the MOS layer away from the gate electrode layer, and theetching protective layer, before being etched, completely covers the MOSlayer.

In some implementations, the TFT further includes an ITO layer. The ITOlayer is disposed on the drain electrode layer and the gate insulationlayer.

In some implementations, the TFT further includes a protective layer.The protective layer is disposed on the source electrode layer, thedrain electrode layer, the MOS layer, and the ITO layer.

In some implementations, the protective layer is made of an organicmaterial, and the protective layer has a thickness of 2˜4 μm.

In a third aspect, a TFT array is provided. The TFT array includes atleast the TFT described in the second aspect.

In some implementations, the TFT array further includes a storagecapacitor, a metal overlap region, and a substrate contact hole.

Advantageous effects: Implementations provide a TFT, a method formanufacturing the same, and a TFT array. By forming the etchingprotective layer on the MOS layer, the MOS layer can be protected by theetching protective layer during etching of the metal electrode layer andthe ITO layer, which can avoid etching the MOS layer by an etchant andthus affecting the performance of the TFT. On the other hand, there isno need to add an extra protective layer for protecting the MOS layer,which is simple in manufacturing process and low in cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart of a method for manufacturing a TFT according toimplementations.

FIG. 2 is a schematic diagram illustrating a process of manufacturing aTFT according to implementations.

FIG. 3 is a schematic structural diagram of a TFT according toimplementations.

FIG. 4 is a schematic structural diagram of a TFT array according toimplementations.

FIG. 5 is a schematic diagram illustrating a process of manufacturing aTFT array according to implementations.

DETAILED DESCRIPTION

In order for clarity and better understanding of purposes, technicalsolutions, and advantages of implementations, implementations will behereinafter described in further detail with reference to theaccompanying drawings. It should be understood that, implementationsdescribed herein are intended for explaining, rather than limiting, thedisclosure.

In the related art, an etchant will destroy a MOS layer during etchingof a source electrode layer and a drain electrode layer, and as aresult, the performance of the entire TFT will be affected. Therefore,in order to solve the above problem, implementations provide a methodfor manufacturing a TFT.

FIG. 1 is a flowchart of a method for manufacturing a TFT according toimplementations. FIG. 2 is a schematic diagram illustrating a process ofmanufacturing a TFT according to implementations. As illustrated in FIG.1 and FIG. 2, the method includes the following.

At block S1, a gate insulation layer 12 is formed on a gate electrodelayer 11.

In order to manufacture the TFT, it is necessary to first select amaterial used for the gate electrode layer 11 of the TFT. The gateelectrode layer 11 may be made of a metal material (such as copper,aluminum, tungsten, gold, silver, etc.) or may be a conductivesemiconductor material (such as doped polysilicon). Then the gateinsulation layer 12 is formed on the gate electrode layer 11. The gateinsulation layer 12 is mainly made of an inorganic material, forexample, an oxide material such as silica or a nitride material such assilicon nitride. The gate insulation layer 12 may be formed on the gateelectrode layer 11 through deposition or coating, for example, physicalvapor deposition (PVD), chemical vapor deposition (CVD), or coating witha coater. As an example, the gate insulation layer 12 may be formed onthe gate electrode layer 11 through plasma CVD (PCVD).

As illustrated in FIG. 1 and FIG. 2, the method further includes thefollowing.

At block S2, a metal-oxide semiconductor (MOS) layer 13 and an etchingprotective layer 14 are sequentially deposited on the gate insulationlayer 12.

In an example, after the gate insulation layer 12 is formed on the gateelectrode layer 11, the MOS layer 13 and the etching protective layer 14are sequentially deposited on the gate insulation layer 12, where theetching protective layer 14 completely covers the MOS layer 13 toprotect the MOS layer 13 from being etched by an etchant whilesource/drain electrodes are being formed. The MOS layer 13 may be madeof a metal oxide such as In—Ga oxide, In—Zn oxide, or In-M-Zn oxide,where M is one of Al, Ga, Y, La, etc., or may be made of a compoundsemiconductor such as SiGe, GaAs, etc. As an example, the MOS layer 13may be made of an amorphous MOS composed of indium, gallium, zinc,aluminum, tin, and oxygen (that is, In—Ga—Zn—O, and “IGZO” for short).An IGZO film has a thickness of 300˜500 Å (Ångström).

It is necessary to etch to obtain a gate electrode channel on the MOSlayer 13, and an etchant used in wet etching (such as mixed acid ofnitric acid, phosphoric acid, and acetic acid, or oxalic acid), or dryetching (such as plasma etching using Cl₂) can etch the MOS layer 13.Therefore, in order not to affect the MOS layer 13 during etching,according to implementations, the etching protective layer 14 isdeposited on the MOS layer 13. The etching protective layer 14 may beany metal layer that cannot be etched by an etchant, such as titanium,tungsten, molybdenum tungsten alloy, or the like. In some examples, theetching protective layer 14 is a titanium metal layer considering that:when used as a protective layer during etching for the gate electrodechannel, the titanium metal layer can protect the MOS layer 13, and onthe other hand, the gate electrode channel thus obtained is easy tocontrol. In addition, a thinner etching protective layer 14 forprotecting the MOS layer 13 is usually more desirable, but if theetching protective layer 14 is made too thin, it is not beneficial toprotecting the MOS layer 13 during etching. Therefore, according toimplementations, the etching protective layer 14 is controlled to be150˜250 Å in thickness. As an example, the etching protective layer 14has a thickness of 250 Å.

As illustrated in FIG. 1 and FIG. 2, the method further includes thefollowing.

At block S3, a metal electrode layer 15 is formed on the gate insulationlayer 12 and the etching protective layer 14.

According to implementations, after the MOS layer 13 and the etchingprotective layer 14 are sequentially deposited on the gate insulationlayer 12, the metal electrode layer 15 is formed on the gate insulationlayer 12 and the etching protective layer 14, where the metal electrodelayer 15 completely covers the etching protective layer 14 and the gateinsulation layer 12. The metal electrode layer 15 has a double-layeredmetal structure including a first metal layer 151 and a second metallayer 152. In some implementations, the first metal layer 151 is analuminum metal layer and the second metal layer 152 is a molybdenummetal layer. The aluminum metal layer, as a main circuit wire of theTFT, is in direct contact with the etching protective layer 14. On theother hand, aluminum is low in resistance, and is beneficial tomanufacturing the TFT without causing pollution. In addition, the firstmetal layer 151, as the main circuit wire of the TFT, is thicker thanthe second metal layer 152. The first metal layer 151 has a thickness of2500˜3000 Å. The second metal layer 152 has a thickness of 300˜500 Å.The metal electrode layer 15 can be formed on the etching protectivelayer 14 and the gate insulation layer 12 through etching, coating,sputtering, etc. As an example, the metal electrode layer 15 can beformed on the etching protective layer 14 and the gate insulation layer12 through sputtering.

As illustrated in FIG. 1 and FIG. 2, the method further includes thefollowing.

At block S4, the metal electrode layer 15 is etched to obtain a sourceelectrode layer 18 and a drain electrode layer 19.

After the metal electrode layer 15 is formed on the gate insulationlayer 12 and the etching protective layer 14, since the MOS layer 13 isprotected by the etching protective layer 14, the metal electrode layer15 can be directly etched by an etchant. During etching, it is onlynecessary to remove a portion of the metal electrode layer 15 that is incontact with the MOS layer 13 (that is, the portion that is in contactwith the etching protective layer 14), and the remaining portion of themetal electrode layer 15 at two ends of the etching protective layer 14is retained, thus obtaining the source electrode layer 18 and the drainelectrode layer 19.

The manner of etching can include wet etching and dry etching. Accordingto implementations herein, the metal electrode layer 15 is etched by anetchant, that is, through wet etching. As an example, the etchant may bea mixed acid solution of nitric acid, phosphoric acid, and acetic acid.Since titanium will not be etched by the etchant, the MOS layer 13 underthe etching protective layer 14 can be protected. By etching the metalelectrode layer 15 with aid of the mixed acid solution, the sourceelectrode layer 18 and the drain electrode layer 19 that have an idealvertical width can be obtained.

In some implementations, operations at block S4 include the following.

At block S41, a photoresist material layer is formed on the metalelectrode layer, and the photoresist material layer is patterned toobtain a photoresist layer.

At block S42, the metal electrode layer is etched, and a pattern of thephotoresist layer is transferred onto the metal electrode layer toobtain the source electrode layer and the drain electrode layer.

In some implementations, after the metal electrode layer 15 is formed onthe gate insulation layer 12 and the etching protective layer 14, thephotoresist material layer is formed on the metal electrode layer 15,and the photoresist material layer is patterned to obtain thephotoresist layer 20, where the photoresist material layer is made of amaterial that will not be etched by an etchant. After the photoresistmaterial layer is patterned to obtain the photoresist layer 20, themetal electrode layer 15 is etched. The etchant will only etch a portionof the metal electrode layer 15 that is not covered by photoresist layer20, and the remaining portion of the metal electrode layer 15 that iscovered by the photoresist layer 20 will not be etched due to protectionby the photoresist layer 20. As such, the pattern of the photoresistlayer 20 is transferred onto the metal electrode layer 15, therebyobtaining the source electrode layer 18 and the drain electrode layer19.

In some implementations, operations at block S41 include the following.

At block S411, the photoresist material layer is formed on the metalelectrode layer.

At block S412, the photoresist material layer is exposed and developedand a part of the photoresist material layer is removed to obtain thephotoresist layer, where the part of the photoresist material layerremoved is on a portion of the metal electrode layer in contact with theetching protective layer.

As an example, the photoresist material layer is first formed on themetal electrode layer 15 through coating. Then the photoresist materiallayer undergoes mask exposure and development with aid of an exposuremachine, and the part of the photoresist material layer, which is on theportion of the metal electrode layer 15 in contact with the etchingprotective layer 14, is removed to obtain the photoresist layer 20. Inother words, after the photoresist material layer is patterned, theportion of the metal electrode layer 15 in contact with the etchingprotective layer 14 has no photoresist layer 20, and the remainingportion of the metal electrode layer 15 at two ends of the etchingprotective layer 14 is protected by the photoresist layer 20. During asubsequent etching of the metal electrode layer 15, the portion of themetal electrode layer 15 in direct contact with the etching protectivelayer 14 will be directly etched due to absence of protection by thephotoresist layer 20, and the remaining portion of the metal electrodelayer 15 at two ends of the etching protective layer 14 will not beetched due to protection by the photoresist layer 20. As such, thesource electrode layer 18 and the drain electrode layer 19 can beobtained at two ends of the etching protective layer 14 respectively. Asan example, the photoresist layer 20 has a thickness of 1.5˜2 μm(micrometer).

In some implementations, after operations at block S412, the followingcan be conducted.

At block S413, the photoresist layer on the metal electrode layer 15 isremoved.

At block S414, an indium tin oxide (ITO) layer 17 is formed on thesource electrode layer 18, the drain electrode layer 19, and the gateelectrode channel.

Since the TFT needs to be coupled with other components (such as astorage capacitor, a pixel capacitor, etc.) to cooperatively drive aliquid crystal pixel, the ITO layer 17 is formed on the source electrodelayer 18, the drain electrode layer 19, and the gate electrode channelafter the source electrode layer 18 and the drain electrode layer 19 areformed at two ends of the MOS layer 13, and via the ITO layer 17, theTFT is coupled with the storage capacitor. As mentioned in the foregoingoperations, the photoresist layer 20 is coated on the metal electrodelayer 15 before the metal electrode layer 15 is etched to obtain thesource electrode layer 18 and the drain electrode layer 19. Therefore,before the ITO layer 17 is formed, the photoresist layer 20 on the metalelectrode layer 15 needs to be removed with aid of a photoresiststripper. Then the ITO layer 17 is formed on the source electrode layer18, the drain electrode layer 19, and the gate electrode channel.

In some implementations, after operations at block S414 are performed,the following can be conducted.

At block S415, a photoresist material layer is formed on the ITO layer17, and the photoresist material layer is patterned to obtain aphotoresist layer 20.

At block S416, the ITO layer 17 is etched, and a pattern of thephotoresist layer 20 is transferred onto the ITO layer 17.

As an example, in order to avoid short circuit between the sourceelectrode layer 18, the drain electrode layer 19, and the gate electrodechannel, after the ITO layer 17 is formed on the source electrode layer18, the drain electrode layer 19, and the gate electrode channel, it isnecessary to etch with the etchant an unnecessary portion of the ITOlayer 17. In order to remove the unnecessary portion of the ITO layer17, a manner that is similar to the foregoing operations of etching themetal electrode layer 15 is adopted. The photoresist material layer isfirst formed on the ITO layer 17, and the photoresist material layer isexposed and developed to pattern the photoresist material layer, therebyobtaining the photoresist layer. Then the ITO layer 17 is etched, suchthat a portion of the ITO layer 17 that has the photoresist layer isretained and the remaining portion of the ITO layer 17 that has nophotoresist layer for protection is removed, and in this way, anecessary portion of the ITO layer 17 can be retained.

As an example, the ITO layer 17 is etched through wet etching. Forexample, the etchant is oxalic acid. Although oxalic acid can also etchthe MOS layer 13, the MOS layer 13 is still completely covered by theetching protective layer 14 in this situation, and the etchingprotective layer 14 cannot be etched by oxalic acid. Therefore, inaddition to protecting the MOS layer 13 during etching of the metalelectrode layer 15, the etching protective layer 14 can protect the MOSlayer 13 during etching of the ITO layer 17.

As illustrated in FIG. 1 and FIG. 2, the method further includes thefollowing.

At block S5, the etching protective layer 14 is etched to expose the MOSlayer 13.

In some implementations, the etching protective layer 14 is used forprotecting the MOS layer 13 from being etched. After etching of themetal electrode layer 15 and etching of the ITO layer 17 are completed,in order to define the gate electrode channel between the sourceelectrode layer 18 and the drain electrode layer 19, the etchingprotective layer 14 needs to be removed to expose the MOS layer 13.

As previously mentioned, the manner of etching can include wet etchingand dry etching. According to implementations, the etching protectivelayer 14 is removed through dry etching to expose the MOS layer 13.Therefore, in addition to inability to be etched by the etchant, theetching protective layer 14 of implementations is required to be able tobe etched through dry etching. As an example, plasma etching usingBCl₃/Cl₂ is performed on the etching protective layer 14 to expose theMOS layer 13 mainly because the titanium metal layer is easily etched byBCl₃/Cl₂ but BCl₃/Cl₂ will not etch the molybdenum metal layer and thealuminum metal layer of the source electrode layer 18 and the drainelectrode layer 19. In such a process, although BCl₃/Cl₂ plasma can alsoetch the MOS layer 13, the MOS layer 13 is completely covered by theetching protective layer 14 and therefore, the MOS layer 13 can beetched only after the etching protective layer 14 is completely etched.By controlling a duration of etching, the MOS layer 13 can be controlledto be etched only by not more than 100 Å after etching of the etchingprotective layer 14 is completed. As previously mentioned, the MOS layer13 has a thickness of 300˜500 Å. Even though etched by 100 Å, the MOSlayer still has a thickness of 200˜400 Å.

As illustrated in FIG. 1 and FIG. 2, the method further includes thefollowing.

At block S6, a protective layer is formed on the source electrode layer18, the drain electrode layer 19, and the gate electrode channel.

In some implementations, after the etching protective layer 14 is etchedto expose the MOS layer 13, it is necessary to form the protective layer16 on the source electrode layer 18, the drain electrode layer 19, andthe gate electrode channel. The protective layer 16 can, on one hand,protect the source electrode layer 18, the drain electrode layer 19, andthe gate electrode channel and on the other hand, position the TFT. Theprotective layer 16 is made of an organic material and has a thicknessof 2˜4 μm. The protective layer 16 can be formed though photoresistcoating, exposure, and development.

Implementations further provide a TFT. The TFT is manufactured with themethod described in the foregoing implementations. FIG. 3 is a schematicstructural diagram of a TFT according to implementations. The TFT 1includes a gate electrode layer 11, a gate insulation layer 12, a MOSlayer 13, an etching protective layer 14, a source electrode layer 18, adrain electrode layer 19, an ITO layer 17, and a protective layer 16.

The gate electrode layer 11 is completely covered by the gate insulationlayer 12. The MOS layer 13 is on a surface of the gate insulation layer12 away from the gate electrode layer 11, and an orthographic projectionof the gate insulation layer 12 on the gate electrode layer 11 falls onthe gate electrode layer 11. The etching protective layer 14 is on asurface of the MOS layer 13 away from the gate electrode layer 11. Theetching protective layer 14 completely covers the MOS layer 13 beforebeing etched, and an orthographic projection of the etching protectivelayer 14 on the gate electrode layer 11 coincides with that of the MOSlayer 13 on the gate electrode layer 11. The source electrode layer 18and the drain electrode layer 19 are on a surface of the gate insulationlayer 12 away from the gate electrode layer 11, and are locatedrespectively at both ends of the MOS layer 13 as well as both ends ofthe etching protective layer 14. A gate electrode channel is definedbetween the source electrode layer 18 and the drain electrode layer 19by etching a metal electrode layer 15. The TFT 1 further includes theITO layer 17. The ITO layer 17 is configured to be coupled with astorage capacitor 2. During actual implementation, when a voltage isapplied to the gate electrode layer 11, a gate voltage generates anelectric field on the gate insulation layer 12. A power line is directedto a surface of the MOS layer 13 from the gate electrode layer 11, andelectric charges are generated on the surface of the MOS layer 13. Asthe gate voltage increases, the MOS layer 13 may be converted from adepletion layer into an electron accumulation layer, to form aninversion layer. When a strong inversion mode is reached, there will becarriers passing through the gate electrode channel between the sourceelectrode layer 18 and the drain electrode layer 19 under action of avoltage. A source-drain voltage increases until a turn-on voltage isreached, thereby driving a pixel in an LCD.

Implementations further provide a TFT array. FIG. 4 is a schematicstructural diagram of a TFT array according to implementations. FIG. 5is a schematic diagram illustrating a process of manufacturing a TFTarray according to implementations. Besides the TFT 1 described above,the TFT array further includes a storage capacitor 2, a metal overlapregion 3, and a substrate contact hole 4.

The TFT 1 has the same structure as the TFT described in the foregoingimplementations, which has been elaborated above. The storage capacitor2 includes a second gate insulation layer 21, the gate insulation layer12, the metal electrode layer 15, the ITO layer 17, and the protectivelayer 16. The gate insulation layer 12 completely covers the second gateinsulation layer 21. The metal electrode layer 15 is disposed on asurface of the gate insulation layer 12 away from the second gateinsulation layer 21. The ITO layer 17 is disposed on a surface of themetal electrode layer 15 away from the gate insulation layer 12. The ITOlayer 17 is coupled with the TFT 1. The protective layer 16 is disposedon a surface of the ITO layer 17 away from the metal electrode layer 15.The protective layer 16 is used for protecting and positioning thestorage capacitor 2. A method for manufacturing the storage capacitor 2corresponds to the method for manufacturing the TFT 1 described in theforegoing implementations. While the gate insulation layer 12 is formedon the gate electrode layer 11, the gate insulation layer 12 is formedon the second gate insulation layer 21. Then the metal electrode layer15 is formed on the gate insulation layer 12. The metal electrode layer15 is patterned, such that a portion of the metal electrode layer 15 incontact with the gate insulation layer 12 on the second gate insulationlayer 21 is retained due to protection by a photoresist layer 20. Thenthe ITO layer 17 is formed on the metal electrode layer 15. The ITOlayer 17 is patterned such that a portion of the ITO layer 17, coupledwith the TFT 1, on the storage capacitor 2 can be retained. Theprotective layer 16 is deposited on the ITO layer 17 and the metalelectrode layer 15, to form the storage capacitor 2.

In some examples, the substrate contact hole 4 includes a fourth gateinsulation layer 41, the gate insulation layer 12, and the ITO layer 17.The gate insulation layer 12 is disposed on the fourth gate insulationlayer 41, and a portion of the gate insulation layer 12 in contact withthe fourth gate insulation layer 41 is etched to expose the fourth gateinsulation layer 41. The ITO layer 17 is disposed on the fourth gateinsulation layer 41 and the gate insulation layer 12. A method formanufacturing the substrate contact hole 4 corresponds to the method formanufacturing the TFT 1 described in the foregoing implementations.After the foregoing operations at block S4, the portion of the gateinsulation layer 12 in contact with the fourth gate insulation layer 41is etched to expose the fourth gate insulation layer 41. Then the ITOlayer 17 is deposited on the fourth gate insulation layer 41 and thegate insulation layer 12, to be coupled with the storage capacitor 2,thereby forming the substrate contact hole 4.

Implementations provide a TFT, a method for manufacturing the same, anda TFT array. The method for manufacturing a TFT includes the following.The gate insulation layer is formed on the gate electrode layer. The MOSlayer and the etching protective layer are sequentially deposited on thegate insulation layer. The metal electrode layer is formed on the gateinsulation layer and the etching protective layer. The metal electrodelayer is etched to form the source electrode layer and the drainelectrode layer. The etching protective layer is etched to expose theMOS layer. By forming the etching protective layer on the MOS layer, theMOS layer can be protected by the etching protective layer while themetal electrode layer and the ITO layer are being etched, which canavoid etching the MOS layer by the etchant and thus affecting theperformance of the TFT. On the other hand, there is no need to add anextra protective layer for protecting the MOS layer, which hasadvantages of simple manufacturing process and low cost.

It is to be understood that the disclosure is not to be limited to thedisclosed embodiments. For those of ordinary skill in the art, variousmodifications and equivalent arrangements can be made according to theforegoing implementations, and all the various modifications andequivalent arrangements shall fall within the protection scope of theappended claims.

1. A method for manufacturing a thin-film transistor (TFT), comprising:forming a gate insulation layer on a gate electrode layer; depositingsequentially on the gate insulation layer a metal-oxide semiconductor(MOS) layer and an etching protective layer; forming a metal electrodelayer on the gate insulation layer and the etching protective layer;etching the metal electrode layer to obtain a source electrode layer anda drain electrode layer; and etching the etching protective layer toexpose the MOS layer.
 2. The method of claim 1, wherein etching themetal electrode layer to obtain the source electrode layer and the drainelectrode layer comprises: forming a photoresist material layer on themetal electrode layer, and patterning the photoresist material layer toobtain a photoresist layer; and etching the metal electrode layer, andtransferring a pattern of the photoresist layer onto the metal electrodelayer to obtain the source electrode layer and the drain electrodelayer.
 3. The method of claim 2, wherein forming the photoresistmaterial layer on the metal electrode layer, and patterning thephotoresist material layer to obtain the photoresist layer comprises:forming the photoresist material layer on the metal electrode layer; andexposing and developing the photoresist material layer and removing apart of the photoresist material layer to obtain the photoresist layer,wherein the part of the photoresist material layer removed is on aportion of the metal electrode layer in contact with the etchingprotective layer.
 4. The method of claim 3, further comprising: afteretching the metal electrode layer to obtain the source electrode layerand the drain electrode layer, removing the photoresist layer on themetal electrode layer; and forming an indium tin oxide (ITO) layer onthe source electrode layer, the drain electrode layer, and a gateelectrode channel.
 5. The method of claim 4, further comprising: afterforming the ITO layer on the source electrode layer, the drain electrodelayer, and the gate electrode channel, forming a photoresist materiallayer on the ITO layer, and patterning the photoresist material layer toobtain a photoresist layer; and etching the ITO layer, and transferringa pattern of the photoresist layer onto the ITO layer.
 6. The method ofclaim 1, further comprising: after etching the etching protective layerto expose the MOS layer, forming a protective layer on the sourceelectrode layer, the drain electrode layer, and a gate electrodechannel.
 7. The method of claim 6, wherein the etching protective layeris a titanium metal layer, and the etching protective layer has athickness of 150˜250 Å.
 8. The method of claim 6, wherein the metalelectrode layer has a double-layered metal structure comprising analuminum metal layer and a molybdenum metal layer, wherein the aluminummetal layer has a thickness of 2500˜3000 Å, and the molybdenum metallayer has a thickness of 300˜500 Å.
 9. A TFT, comprising: a gateelectrode layer; a gate insulation layer disposed on the gate electrodelayer; a MOS layer disposed on the gate insulation layer; an etchingprotective layer disposed on the MOS layer; and a source electrode layerand a drain electrode layer disposed on the gate insulation layer andspaced apart at two ends of the etching protective layer.
 10. The TFT ofclaim 9, wherein the etching protective layer is disposed on a surfaceof the MOS layer away from the gate electrode layer, and the etchingprotective layer, before being etched, completely covers the MOS layer.11. The TFT of claim 9, further comprising an ITO layer disposed on thedrain electrode layer and the gate insulation layer.
 12. The TFT ofclaim 11, further comprising a protective layer disposed on the sourceelectrode layer, the drain electrode layer, the MOS layer, and the ITOlayer.
 13. The TFT of claim 12, wherein the protective layer is made ofan organic material, and the protective layer has a thickness of 2˜4 μm.14. A TFT array comprising at least a TFT, the TFT comprising: a gateelectrode layer; a gate insulation layer disposed on the gate electrodelayer; a MOS layer disposed on the gate insulation layer; an etchingprotective layer disposed on the MOS layer; and a source electrode layerand a drain electrode layer disposed on the gate insulation layer andspaced apart at two ends of the etching protective layer.
 15. The TFTarray of claim 14, further comprising a storage capacitor, a metaloverlap region, and a substrate contact hole.
 16. The TFT array of claim14, wherein the etching protective layer is disposed on a surface of theMOS layer away from the gate electrode layer, and the etching protectivelayer, before being etched, completely covers the MOS layer.
 17. The TFTarray of claim 14, wherein the TFT further comprises an ITO layerdisposed on the drain electrode layer and the gate insulation layer. 18.The TFT array of claim 17, wherein the TFT further comprises aprotective layer disposed on the source electrode layer, the drainelectrode layer, the MOS layer, and the ITO layer.
 19. The TFT array ofclaim 18, wherein the protective layer is made of an organic material,and the protective layer has a thickness of 2˜4 μm.